Specification Details & Pinouts
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USB4 2.0 Specification: 80Gbps & 240W Complete Reference
USB4 2.0 (published September 2022) doubles the maximum bandwidth of USB4 from 40Gbps to 80Gbps while maintaining backward compatibility with USB 3.2, USB 2.0, and Thunderbolt 3/4.
Key Specifications
| Parameter | USB4 1.0 | USB4 2.0 |
|---|---|---|
| Max Data Rate | 40Gbps | 80Gbps |
| Signaling | Gen 3 (20Gbps/lane) | Gen 4 (40Gbps/lane) |
| Lanes | 2 (bidirectional) | 2 (bidirectional) |
| Power Delivery | 100W (20V/5A) | 240W (48V/5A EPR) |
| PCIe Tunneling | Gen 3 x4 (32Gbps) | Gen 4 x4 (64Gbps) |
| DisplayPort | DP 1.4a (HBR3) | DP 2.1 (UHBR20) |
| Host Interface | PCIe 3.0 x4 | PCIe 4.0 x4 |
Asymmetric Bandwidth Modes
USB4 2.0 introduces asymmetric lane allocation for the first time in USB history:
- 120Gbps + 40Gbps: One direction gets 3 lanes, the other gets 1 lane
- 80Gbps + 80Gbps: Symmetric Gen 4 x2 (default mode)
- 60Gbps + 20Gbps: Display-heavy workloads (3:1 allocation)
EPR (Extended Power Range) Implementation
USB PD 3.1 EPR requires:
- E-Marker chip reporting Vbus_max ≥ 48V and I_max ≥ 5A
- Source voltage range: 15V-28V (SPR) and 29V-48V (EPR)
- Hard reset required before entering EPR mode
- Cable must support 240W continuous (not just peak)
Pin Assignments (USB Type-C)
| Pin | Name | USB4 2.0 Function |
|---|---|---|
| A1, B1, A12, B12 | GND | Ground return |
| A4, B4, A9, B9 | Vbus | 48V EPR power delivery |
| A2, A3, A10, A11 | SSTX/RX | Gen 4 high-speed data (40Gbps/lane) |
| A5 | CC1 | Configuration channel (BMC PD) |
| A6, A7 | DP/DN | USB 2.0 legacy (480Mbps) |
| A8 | SBU1 | Sideband use (DP AUX or analog audio) |
Reference: USB4 Specification Rev 2.0, September 2022. USB PD Rev 3.1 V1.7, January 2023.